2024/11/20

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2024-11-20 06:21:07 +0100ChaiTRex(~ChaiTRex@user/chaitrex) ChaiTRex
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2024-11-20 04:41:57 +0100rekahsoft(~rekahsoft@bras-base-orllon1103w-grc-06-76-69-85-220.dsl.bell.ca) rekahsoft
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2024-11-20 04:23:16 +0100vanishingideal(~vanishing@user/vanishingideal) vanishingideal
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2024-11-20 04:13:59 +0100 <edwardk> hellwolf: re the export list, you can of course skip using an explicit export list. the least amount of code is no code at all there.
2024-11-20 04:02:05 +0100 <Axman6> any python devs know of a python equivalent to insertWith max k v dict?
2024-11-20 03:36:41 +0100peterbecich(~Thunderbi@syn-047-229-123-186.res.spectrum.com) peterbecich
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2024-11-20 02:59:18 +0100Alleria(~Alleria@user/alleria) Alleria
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2024-11-20 02:42:03 +0100Alleria_(~Alleria@user/alleria) Alleria
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2024-11-20 02:31:21 +0100euleritian(~euleritia@ip4d16fc9f.dynamic.kabel-deutschland.de)
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2024-11-20 02:17:48 +0100JuanDaugherty(~juan@user/JuanDaugherty) JuanDaugherty
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2024-11-20 02:05:07 +0100 <Axman6> I love it, I wish we'd use it at work, VHDL is such a horrific language
2024-11-20 02:03:44 +0100 <hellwolf> Axman6: yes I should checkout clash, heard a lot about it...
2024-11-20 02:03:29 +0100 <hellwolf> Yea, I wonder if there is better way of doing that 'True 'False thing :) I guess the domain I am dealing with spared me with non octal trite...
2024-11-20 02:02:17 +0100 <Axman6> hellwolf: you might also want to look at how Clash does numbers
2024-11-20 02:00:06 +0100 <Axman6> the DSPs we have do 18x25 bit multiplications (IIRC)
2024-11-20 01:59:57 +0100 <geekosaur> …everything old is new again
2024-11-20 01:59:41 +0100 <Axman6> FPGAs
2024-11-20 01:59:25 +0100 <geekosaur> pdp7? 😛
2024-11-20 01:58:44 +0100 <Axman6> hellwolf: why limit it to multiples of 8? We use a lot of 18 bit ints at work =)