2026/05/25

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2026-05-25 18:09:29 +0000emilym(~Thunderbi@user/emilym) (Ping timeout: 245 seconds)
2026-05-25 18:08:58 +0000 <int-e> tomsmeding: It's a bit more complicated than the basic WRC example because in the GHC runtime reading old values is generally okay. So to actually cause trouble it has to read not-yet-propagated ("future") values instead.
2026-05-25 18:02:36 +0000merijn(~merijn@host-cl.cgnat-g.v4.dfn.nl) (Ping timeout: 252 seconds)
2026-05-25 17:59:04 +0000Eoco(~ian@128.101.131.218) Eoco
2026-05-25 17:58:02 +0000merijn(~merijn@host-cl.cgnat-g.v4.dfn.nl) merijn
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2026-05-25 17:55:56 +0000 <tomsmeding> (now actually afk)
2026-05-25 17:55:43 +0000 <tomsmeding> (funny sidenote: ARMv7 allowed this behaviour; an early spec for ARMv8 also did, but it was considered too hard to reason about and actual silicon manufacturers didn't end up using the flexibility, so the ARMv8 spec was revised to require causality)
2026-05-25 17:55:36 +0000ricardomaps(~ricardoma@179.154.171.223)
2026-05-25 17:50:40 +0000tomsmedingis afk for a while
2026-05-25 17:50:37 +0000sm__(~sm@2601:644:8280:ec80:f80f:4c71:49ff:3397)
2026-05-25 17:50:18 +0000 <tomsmeding> this stuff is way too subtle
2026-05-25 17:50:06 +0000 <int-e> it was clearer in my head ;)
2026-05-25 17:49:53 +0000 <tomsmeding> ah! There we go
2026-05-25 17:48:53 +0000 <int-e> tomsmeding: https://paste.tomsmeding.com/IjEujBEA
2026-05-25 17:48:07 +0000 <tomsmeding> because those two formulations sound too close in meaning to me :p
2026-05-25 17:47:46 +0000 <int-e> aha! let me rephrase those...
2026-05-25 17:47:06 +0000merijn(~merijn@host-cl.cgnat-g.v4.dfn.nl) (Ping timeout: 242 seconds)
2026-05-25 17:46:41 +0000 <tomsmeding> you're making a distinction between "evaluate t2 to r1" and "evaluate t2, get r1"?
2026-05-25 17:46:23 +0000 <int-e> x is t1
2026-05-25 17:46:16 +0000 <int-e> the `1` value is `r1`; y is t2.
2026-05-25 17:45:44 +0000 <tomsmeding> (if the read from y yielded 0, then x = 0 is perfectly fine and unsurprising)
2026-05-25 17:45:16 +0000 <tomsmeding> (i.e. your analogue to "read y, yielding 1" is implicit, and I'd like it to be explicit)
2026-05-25 17:45:15 +0000 <int-e> while if it read it from t1 then release ordering from thread 1 would ensure that tht data is there
2026-05-25 17:44:54 +0000 <int-e> yeah. but it gets it from t2, written by thread 2, and only causality links it to the local heap data of thread 1
2026-05-25 17:44:14 +0000 <tomsmeding> int-e: still, the point here is that thread 3 does get the <IND r1>, right? If it doesn't, then it just evaluates t2 to r1 itself and that's that
2026-05-25 17:43:10 +0000 <tomsmeding> nah